During the last several decades, the issue of error correction and detection has great practical importance. Error detection and correction are the abilities to detect errors that are made due to scratches or other impairments in the course of the transmission from the transmitter to the receiver, meanwhile enable localization and correcting of the errors. An error correcting code (ECC) is therefore contributed to the above. ECC is used in computer data storage, for example flash memory and dynamic RAM, and in data transmission. Examples include Hamming code, Reed-Solomon code, Bose-Chaudhuri-Hocquengham (BCH) code, Reed-Muller code, Binary Golay code, convolutional code, and turbo code. The simplest error correcting codes can correct single-bit errors and detect double-bit errors. Other codes can detect or correct multi-bit errors. ECC provides greater data accuracy and system uptime by protecting against possible errors in computer memory.
FIG. 1 illustrates virtual to physical address translation in a flash file system according to the prior art. Physical address space 13 is composed of physical units 111 that are actually the erase blocks, i.e., the smallest chunks that can be erased. Each physical unit 111 contains one or more physical pages 113, where a page is the smallest chunk that can be written. A virtual address space 11 is composed of virtual units 121 that have the same size as the physical units. Each virtual unit contains one or more virtual pages 123, having the same size as physical pages 113. When a virtual address is provided by an application, for reading or writing, the virtual unit number to which that address belongs is extracted from the virtual address. As stated above, a physical page is a minimum unit for programming data-reading. In other words, the prior art is not able to process the size of the stored data less than that of a page, normally 512 bytes in conventional flash memory or 2048 bytes in NAND flash memory, and relatively influences the overall reliability and performance of the flash memory.
In addition, the time required for error correction is related to the length of error correction bits and that of data bits being processed during any error correcting cycle. In general, great efficiency is achieved by processing a longer bit length of ECCs in the erroneous area, i.e., where the errors occur the most, and vice versa. However, in previous memory management circuits, such as the flash memory system of U.S. Pat. No. 5,937,425, the overhead consumption of error correction was relatively high because the ECC bit length and page size are fixed by industry standard. To overcome the limitation of prior art, it is desirable to provide a flash memory system and a controlling method for better utilization of the capacity of a page and efficient allocation of ECCs.